Author(s)

Sheng Lin

Advisor(s)

Fabrizio Lombardi (1955-)

Contributor(s)

Kim Yong-Bin, Gunar Schirner

Date of Award

2011

Date Accepted

5-2011

Degree Grantor

Northeastern University

Degree Level

Ph.D.

Degree Name

Doctor of Philosophy

Department or Academic Unit

College of Engineering. Department of Electrical and Computer Engineering.

Keywords

Circuit Robustness, Memory Stability, Nanometric Circuit Design

Disciplines

Engineering

Abstract

The stability of storage element circuits in the nanoscale era, such as memories and latches is evaluated and new circuit configurations for stability improvement are proposed in this dissertation. The stability and robustness of a given memory cell are usually evaluated by analyzing both static and dynamic behaviors during typical operation. In this dissertation, a 9T CMOS SRAM cell design at 32nm is first presented to improve static stability, power dissipation, and delay compared to the conventional SRAM cell as well as a detailed comparison with other designs found in the technical literature. Moreover, a dual-diameter Carbon Nanotube-based SRAM cell configuration with different threshold voltages is then designed; this cell shows significant improvements compared to its CMOS counterpart in terms of power consumption and stability.

Two memory cell configurations at 32nm CMOS technology for improving dynamic stability are then proposed in this dissertation and simulation results show significant improvement in dynamic stability. In this work, a comprehensive treatment (model, analysis and design) for hardening storage elements against a soft error resulting in multiple node upsets is also presented. A novel 13T memory cell configuration is proposed and simulated to show a significantly better tolerance to the likely multiple node upset. Simulation results have confirmed that the proposed memory cell accomplish an excellent soft error tolerance through hardening and an impressive power-delay product compared with the other commonly used hardened design.

For the latch, the stability of a latch cell is only judged by the Critical Charge (Qcrit) when the latch is not transparent. Three new hardened designs for CMOS latches at 32nm feature size are proposed. For the latch design, a novel design metric (QPAR) is introduced to assess the overall design effectiveness such as area, performance, power, and soft error tolerance. It has been shown in the dissertation that the proposed latch achieved the best overall performance compared with the existing designs. The multiple node upset analysis is also extended to hardened latches; it is shown that the latch with the highest critical charge has also the best tolerance to multiple node upsets

Document Type

Dissertation

Rights Holder

Sheng Lin


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