Advisor(s)
Miriam E. Leeser
Contributor(s)
Jennifer G. Dy, Brie Howley
Date of Award
2010
Date Accepted
4-2010
Degree Grantor
Northeastern University
Degree Level
M.S.
Degree Name
Master of Science
Department or Academic Unit
College of Engineering, Department of Electrical and Computer Engineering
Keywords
electrical engineering, clustering, FPGA, pulse deinterleaving
Disciplines
Electrical and Computer Engineering | Engineering
Abstract
Incremental clustering is the unsupervised classification of dynamic streaming data samples into related groups called clusters. The process considers each data point only once so it is applicable to real-time problems requiring low latency solutions. One such application is the deinterleaving of radar pulse streams in an electronic warfare (EW) systems. Given a single stream of combined radar signals deinterleaving attempts to identify individual radar emitters based on characteristics of the received signal.
This thesis focuses on implementing an incremental clustering algorithm on a field-programmable gate array (FPGA) for the purposes of radar pulse deinterleaving. We introduce ICED, an algorithm for the I ncremental Clustering of Evolving Data, and discuss the details of implementing it in an FPGA. Experimental results show the applicability of the algorithm to the real-time requirements of EW pulse deinterleaving. The resulting design provides a 16 cluster implementation that consumes 70% of a Xilinx Virtex-5 SX95T FPGA and requires a processing latency of 420ns, resulting in a 39x speedup over software.
Document Type
Master's Thesis
Rights Information
copyright 2010
Rights Holder
Scott Michael Bailie
Permanent URL
Recommended Citation
Bailie, Scott Michael, "An FPGA implementation of incremental clustering for radar pulse deinterleaving" (2010). Electrical and Computer Engineering Master's Theses. Paper 43. http://hdl.handle.net/2047/d20000900
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