Advisor(s)

Yong-Bin Kim

Contributor(s)

Fabrizio Lombardi, Gunar Schirner

Date of Award

2010

Date Accepted

5-2010

Degree Grantor

Northeastern University

Degree Level

M.S.

Degree Name

Master of Science

Department or Academic Unit

College of Engineering, Department of Electrical and Computer Engineering

Keywords

electrical engineering, CMOS latched comparator, dynamic, high-speed, low-offset, low-power

Disciplines

Electrical and Computer Engineering | Engineering

Abstract

A new fully dynamic latched comparator which shows lower offset voltage and higher load drivability than the conventional dynamic latched comparators has been designed. With two additional inverters inserted between the input- and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage was improved and the complementary version of the output-latch stage, which has bigger output drive current capability at the same area, was implemented. As a result, the circuit shows up to 19% less offset voltage and 62% less sensitivity of the delay versus the input voltage difference (delay/log(Vin)), which is about 17ps/decade, than the conventional double-tail latched comparators at approximately the same area and power consumption. Along with the proposed design, this thesis provides a comprehensive review about a variety of traditional dynamic latched comparator designs - in terms of performance, power, area and input-referred offset voltage.

Document Type

Master's Thesis

Rights Information

copyright 2010

Rights Holder

HeungJun Jeon

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