Advisor(s)
Miriam E. Leeser
Contributor(s)
David R. Kaeli, Charles A. DiMarzio
Date of Award
2008
Date Accepted
8-2008
Degree Grantor
Northeastern University
Degree Level
M.S.
Degree Name
Master of Science
Department or Academic Unit
College of Engineering. Department of Electrical and Computer Engineering.
Keywords
Electrical and computer engineering, Phase unwrapping
Subject Categories
Field programmable gate arrays, Graphics processing units
Disciplines
Engineering
Abstract
Phase unwrapping is the process of converting discontinuous phase data into a continuous image. This procedure is required by any imaging technology that uses phase data such as MRI, SAR or OQM microscopy. Such algorithms often take a significant amount of time to process on a general purpose computer, rendering it difficult to process large quantities of information. This thesis focuses on implementing a specific phase unwrapping algorithm known as Minimum LP norm unwrapping on a Field Programmable Gate Array (FPGA) and a Graphics Processing Unit (GPU) for the purpose of acceleration. The computation required involves a matrix preconditioner (based on a DCT transform) and a conjugate gradient calculation along with a few other matrix operations. These functions are partitioned to run on the host or the accelerator depending on the capabilities of the accelerator. The trade-offs between the two platforms are analyzed and compared to a General Purpose Processor (GPP) in terms of performance, power and cost.
Document Type
Master's Thesis
Rights Information
Copyright 2008
Rights Holder
Sherman Braganza
Permanent URL
Recommended Citation
Braganza, Sherman, "Phase unwrapping on recongurable hardware and graphics processors" (2008). Electrical and Computer Engineering Master's Theses. Paper 19. http://hdl.handle.net/2047/d10017252
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