IRis

Title

A 45nm CMOS, low jitter, all-digital delayed locked loop with a circuit to dynamically vary phase to achieve fast lock

Author(s)

Soumya Shivakumar Begur, Northeastern University

Advisor(s)

Yong-Bin Kim

Contributor(s)

Fabrizio Lombardi, Gunar Schirner

Date of Award

2011

Date Accepted

10-2011

Degree Grantor

Northeastern University

Degree Level

M.S.

Degree Name

Master of Science

Department or Academic Unit

College of Engineering, Department of Electrical and Computer Engineering

Keywords

computer engineering, process, voltage and temperature (PVT), digital delay locked loop (DLL)

Disciplines

Computer Engineering

Abstract

The objective of the thesis is to address the problem of clock skew between two different clock domains in modern day microprocessors due to the process, voltage and temperature (PVT) variations. In order to mitigate the misalignment of the clocks in the different clock domains, a delay line is added in all but the reference clock domain. These delay lines add or subtract the delay (as necessary) to keep the clocks continuously aligned to a common reference clock delay. This ensures error free data transfer between any two clock domains.

A novel Digital Delay Locked Loop (DLL) design is proposed to achieve short locking time by having a separate circuitry for fast lock in the DLL. The fast lock mechanism can be switched o and the power dissipation can be returned to normal levels after the DLL has locked. A separate fine-delay block makes the proposed DLL have ultra-low jitter after lock. The results show that the proposed DLL, implemented in 45nm CMOS technology, needs only 24 cycles to correct (i.e. to lock) for 500ps clock skew when compared to more than 38 lock cycles for a conventional DLL without the fast lock mechanism. A Monte-Carlo simulation yielded a RMS jitter and peak-to-peak jitter values after lock of 5.26ps and 10.57ps respectively. Average power consumption before lock is <425uW with this number falling to><335uW after lock. The frequency of operation of the proposed DLL is 280MHz>- 1.63GHz and can be used for a variety of applications which require precise time intervals.

Document Type

Master's Thesis

Rights Information

copyright 2011

Rights Holder

Soumya Shivakumar Begur

Permanent URL

http://hdl.handle.net/2047/d20002106

Recommended Citation

Begur, Soumya Shivakumar, "A 45nm CMOS, low jitter, all-digital delayed locked loop with a circuit to dynamically vary phase to achieve fast lock" (2011). Computer Science Master's Theses. Paper 5. http://hdl.handle.net/2047/d20002106