Advisor(s)

David R. Kaeli

Contributor(s)

Mehdi B. Tahoori, Waleed M. Meleis

Date of Award

2010

Date Accepted

3-2010

Degree Grantor

Northeastern University

Degree Level

Ph.D.

Degree Name

Doctor of Philosophy

Department or Academic Unit

College of Engineering. Department of Computer and Electrical Engineering.

Keywords

computer engineering, abstraction, vulnerability

Subject Categories

Fault-tolerant computing

Disciplines

Computational Engineering

Abstract

Tolerance to the effects of transient faults is now a primary design constraint for all major microprocessors. Chip vendors typically set a failure rate target for each design and strive to maximize performance subject to this constraint. To validate that a design meets the failure rate target, vendors perform extensive pre- and post- silicon analysis. One step in this analysis is measuring the Architectural Vulnerability Factor (AVF) of each on-chip structure. The AVF of a hardware structure is the probability that a fault in the structure will affect the output of a program. While AVF generates meaningful insight into system behavior, it does not express vulnerability in terms of the system stack (hardware, virtual machine, user program, etc.), limiting the amount of insight that can be generated. To remedy this, we propose the System Vulnerability Stack, a framework to calculate a vulnerability factor at each level of the system stack. These vulnerability factors can be used individually or combined to generate a system-level AVF measurement. In this thesis, we first establish a rigorous theoretical and mathematical basis for the vulnerability stack, and introduce the simulation framework through which the individual vulnerability factors can be measured. We then present several methods by which the vulnerability stack can influence system design. We show that the Program Vulnerability Factor can be used during the software design cycle to increase the robustness of a software program. We also show that the Hardware Vulnerability Factor can improve the hardware design cycle, improving the robustness of hardware as well as allowing better assessment of chip failure rates at design time. Finally, we demonstrate that the concepts behind stack can be applied at runtime to improve online monitoring of system vulnerability.

Document Type

Dissertation

Rights Information

Copyright 2010

Rights Holder

Vilas Keshav Sridharan


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