Abstract

Division and square root are important operations in any high performance signal processing applications. We have implemented floating point division and square root based on Taylor series for the variable precision floating point library developed at the Reconfigurable Computing Laboratory at Northeastern. Our result shows that they are very well suited to FPGA implementations, and lead to a good tradeoff of area and latency. We implemented a floating-point K-means clustering algorithm and applied it to multispectral satellite images. The mean update is moved from host to FPGA hardware with the new fp_div module to reduce the communication between host and FPGA board and further accelerate the runtime. We are also working on QR factorization using both floating point divide and square root.

Notes

Poster presented at the 2007 Thrust R3A Parallel Hardware Implementation for Fast Subsurface Detection Conference

Keywords

FPGA, QR factorization, operations, floating point library

Subject Categories

Signal processing--Digital techniques--Mathematics

Disciplines

Computer Engineering

Publisher

Bernard M. Gordon Center for Subsurface Sensing and Imaging Systems (Gordon-CenSSIS)

Publication Date

2007

Rights Holder

Bernard M. Gordon Center for Subsurface Sensing and Imaging Systems (Gordon-CenSSIS)



Click button above to open, or right-click to save.

Share

COinS